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| this is information on a product in full production. february 2017 docid029768 rev 2 1/65 ST25R3910 mid-range hf reader with 0.7 w supporting aat datasheet - production data features ? close loop adjustment of ask modulation for accurate control of modula tion depth in case of iso-14443b protocol ? low power (3.5 a) nfc target mode ? am/pm demodulator ? accurate rf envelope measurement (8-bit a/d converter) ? high output power at 3.3 v power supply: ? up to 700 mw in case regulator is externally shorted ? up to 500 mw in case of differential output when antenna trimming is used ? up to 125 mw in case of single ended output when antenna trimming is used ? squelch for gain reduction, to compensate for noise generated by tag processing ? automatic antenna tuning (aat) ? transparent mode ? amplitude and phase measurement ? supporting 13.56 mhz and 27.12 mhz quartz oscillator with fast start-up ? supply voltage range from 2.4 to 3.6 v ? wide temperature range: -40 oc to 85 oc ? package: 32-pin qfn (5x5mm) description the ST25R3910 is a high performance 13.56 mhz rfid reader, with two differential, low impedance (1.5 ohm) antenna drivers. these drivers are unmatched, allowing the ST25R3910 to deliver up to eight times the output power of a standard hf reader ic using the same power supply voltage, and reducing in half the power consumption at the same output power. the ST25R3910 can operate already at 2.4 v, with a low power operating mode of 5 ma, making it perfectly suited for portable or battery-powered applications. for applications where high power is required the ST25R3910 can deliver up to 700 mw, thus avoiding the need for complex external booster circuitry. the component count and complexity of the design is further reduced through automatic modulation depth adjustment. the analog front end (afe) is complemented by a highly integrated data framing engine for both iso-14443 a and b. this includes data rates up to 848 kbit/s, with all framing and synchronization tasks on board. this enables to build a complete hf rfid reader using only a low end mcu. the ST25R3910 supports reader to tag and peer to peer communication using the nfcip-1 active communication mode with a 106 kbps data rate. other standard and custom protocols, such as iso-15693 or felica ? can be implemented via transparent mode. the ST25R3910 features a spi, which enables bi-directional communication with the external microcontroller. the ST25R3910 also features the automatic antenna tuning (aat) technology, enabling the reader to re tune itself to deliver maximum output at 13.56 mhz, when the surroundings detune the antenna. qfn32 www.st.com
contents ST25R3910 2/65 docid029768 rev 2 contents 1 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.1 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.2 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.3 phase and amplitude detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.4 a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.5 external field detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.6 quartz crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.7 power supply regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.8 por and bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.9 iso-14443 and nfcip-1 framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.10 fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.11 control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.12 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2.1 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.2.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.2.4 a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.2.5 phase and amplitude detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.2.6 external field detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.2.7 quartz crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.2.8 power supply, regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.2.9 communication with an external microcon troller . . . . . . . . . . . . . . . . . . 17 1.2.10 direct commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.2.11 operating sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.2.12 iso-14443 reader operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.2.13 nfcip-1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.2.14 am modulation depth: definition and calib ration . . . . . . . . . . . . . . . . . . 30 1.2.15 antenna tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.3 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.3.1 iso mode definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.3.2 operation control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1.3.3 configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 docid029768 rev 2 3/65 ST25R3910 contents 4 1.3.4 configuration register 3 (iso-14443a and nfc) . . . . . . . . . . . . . . . . . 40 1.3.5 configuration register 4 (i so-14443b) . . . . . . . . . . . . . . . . . . . . . . . . . 41 1.3.6 configuration register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 1.3.7 receiver configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 1.3.8 mask interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 1.3.9 interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 1.3.10 fifo status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 1.3.11 collision register (iso-14443 a only) . . . . . . . . . . . . . . . . . . . . . . . . . . 45 1.3.12 number of transmitted bytes register 0 . . . . . . . . . . . . . . . . . . . . . . . . 46 1.3.13 number of transmitted bytes register 1 . . . . . . . . . . . . . . . . . . . . . . . . 46 1.3.14 a/d output register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 1.3.15 antenna calibration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 1.3.16 external trim register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 1.3.17 modulation depth definition register . . . . . . . . . . . . . . . . . . . . . . . . . . 49 1.3.18 modulation depth display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 1.3.19 antenna driver am modu lated level definition regist er . . . . . . . . . . . . 50 1.3.20 antenna driver non-modulated level de finition register . . . . . . . . . . . 50 1.3.21 nfcip field detection threshold register . . . . . . . . . . . . . . . . . . . . . . 51 1.3.22 regulator display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 1.3.23 regulated voltage definition register . . . . . . . . . . . . . . . . . . . . . . . . . . 53 1.3.24 receiver state display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.3 dc/ac characteristics for digital inputs and outputs . . . . . . . . . . . . . . . . 59 3.3.1 cmos inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.3.2 cmos outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.1 qfn32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 contents ST25R3910 4/65 docid029768 rev 2 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 docid029768 rev 2 5/65 ST25R3910 list of tables 5 list of tables table 1. serial data interface (4-wire interface) signal lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 2. spi operation patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 3. intr output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 4. direct commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 5. nfc p2p timings implemented in ST25R3910. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 6. setting mod bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 7. registers map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 8. iso mode definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 9. operation control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 10. configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 11. configuration register 3 (iso-14443a and nfc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 12. configuration register 4 (iso-14 443b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 13. io configuration register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 14. receiver configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 15. mask interrupt registerr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 16. interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 17. fifo status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 18. collision register (iso-14443a only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 19. number of transmitted bytes register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 20. number of transmitted bytes register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 21. a/d output register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 22. antenna calibration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 23. external trim register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 24. modulation depth definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 25. modulation depth display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 26. antenna driver am modulated level definition regi ster . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 27. antenna driver non-modulated level definition register . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 28. nfcip field detection threshold register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 29. target activation threshold as seen on rfi1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 30. collision avoidance thre shold as seen on rfi1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 31. regulators display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 32. regulated voltage definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 33. regulated voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 34. receiver state display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 35. rssi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 36. ST25R3910 pin definitions - qfn32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 37. electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 38. electrostatic discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 39. temperature ranges and storage conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 40. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 41. cmos inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 42. cmos outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 43. electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 44. qfn32 5 mm x 5 mm dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 45. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 46. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 list of figures ST25R3910 6/65 docid029768 rev 2 list of figures figure 1. ST25R3910 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. minimum configuration with single sided antenna driving (including emc filter) . . . . . . . . 10 figure 3. minimum configuration with di fferential antenna driving (including emc filter). . . . . . . . . . 11 figure 4. exchange of signals with microcontr oller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 figure 5. spi communication: writing a single byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 6. spi communication: writing multiple bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 7. spi communication: reading a single byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 8. spi communication: loading of fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 figure 9. spi communication: reading of fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 figure 10. spi communication: direct command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 11. connection of trimming capacitors to the antenna lc tank . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 12. ST25R3910 qfn32 pinout (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 13. qfn32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 docid029768 rev 2 7/65 ST25R3910 functional overview 35 1 functional overview the ST25R3910 is suitable for applications where the reader antenna is directly driven (no 50 ? cable). several unique features make it especially suitable for low power and battery powered applications. 1.1 block diagram the block diagram is shown in figure 1 . figure 1. ST25R3910 block diagram 1.1.1 transmitter the transmitter incorporates drivers that dr ive external antenna through pins rfo1 and rfo2. single sided and differential driving is possible. the transmitter block additionally contains a sub-block that modulates transmitted signal (ook or configurable am modulation). 0 6 9 6 7 5 / r j l f ; 7 2 ; 7 , 5 ) 2 5 ) , 5 ) , 6 3 , 5 ) 2 5 h f h l y h u 7 u d q v p l w w h u 5 h j x o d w r u v $ ' f r q y h u w h u ; 7 $ / r v f l o o d w r u 3 2 5 d q g % l d v ( [ w h u q d o i l h o g g h w h f w r u 3 k d v h d q g d p s o l w x g h g h w h f w r u ) , ) 2 & r q w u r o o r j l f 6 3 , ) u d p l q j functional overview ST25R3910 8/65 docid029768 rev 2 the ST25R3910 transmitter is intended to directly drive antennas (without 50 ? cable, usually antenna is on the same pcb). operation with 50 ? cable is also possible, but in that case some of the advanced features are not available. 1.1.2 receiver the receiver detects tag modulation superimposed on the 13.56 mhz carrier signal. the receiver contains two receive chains (one for am and another for pm demodulation) composed of a peak detector followed by two gain and filtering stages and a final digitizer stage. the filter characteristics are adjusted to optimize performance for each mode and bit rate (sub-carrier frequencies from 212 khz to 848 khz are supported). the receiver chain inputs are the rfi1 and rfi2 pins. the receiver chain incorporates several features that enable reliable operation in challenging phase and noise conditions. 1.1.3 phase and am plitude detector the phase detector is observing the phase diff erence between the transmitter output signals (rfo1 and rfo2) and the receiver input signals (rfi1 and rfi2). the amplitude detector is observing the amplitude of the receiver input signals (rfi1 and rfi2) via self-mixing. the amplitude of the receiver input signals (rfi 1 and rfi2) is directly proportional to the amplitude of the antenna lc tank signal. the phase detector and the amplitude detector can be used for the following purposes: ? pm demodulation, by observing rfi1 and rfi2 phase variation ? average phase difference between rfox pins and rfix pins is used to check and optimize antenna tuning and inductive wakeup via the mcu ? amplitude of signal present on rfi1 and rfi2 pins is used to check and optimize antenna tuning 1.1.4 a/d converter the ST25R3910 contains a built in analog to digital (a/d) converter. its input can be multiplexed from different sources and is used in several applications (measurement of rf amplitude and phase, calibration of modulation depth?). the result of the a/d conversion is stored in a register and can be read via spi. 1.1.5 external field detector the external field detector is a low power block switched on in nfcip ta rget mode to detect the presence of the initiato r field, and also used during the nfcip collision avoidance procedure. 1.1.6 quartz crystal oscillator the quartz crystal oscillator can operate with 13.56 mh z and 27.12 mhz crystals. at start-up the transconductance of the oscillator is increa sed to achieve a fast start-up. the start-up time varies with crystal type, temperatur e and other para meters, hence the oscillator amplitude is observed and an interrupt is sent when stable oscillato r operation is reached. the oscillator block also provides a clock signal to the external microcontroller (mcu_clk), according to the settings in the control register. docid029768 rev 2 9/65 ST25R3910 functional overview 35 1.1.7 power supply regulators integrated power supply regulators ensure a high power supply rejection ratio for the complete reader system. if the reader s ystem psrr has to be improved, the command adjust regulators is sent. as a result of this command, the power supply level of v dd is measured in maximum load conditions and the regulated voltage reference is set 250 mv below this measured level to assure a stable regulated supply. the resulting regulated voltage is stored in a register. it is also po ssible to define regulated voltage by writing a configuration register. to decouple any noise sources from different parts of the ic there are three regulators integrated with separated ex ternal blocking capacitors (the regulated voltage of all of them is the same). one regula tor is for the analog blocks,the other is for the antenna drivers. logic and digital i/o pads are supplied directly from v dd (negative supply pin for logic and digital i/o is separated to avoid coupling of logic induced noise in the substrate). this block additionally generates a refe rence voltage for the analog processing (agd - analog ground). this voltage also ha s an associated external buffer capacitor. 1.1.8 por and bias this block provides the bias current and the re ference voltages to all other blocks. it also incorporates a power on reset (por) circuit th at provides a reset at power-up and at low supply voltage levels. 1.1.9 iso-14443 and nfcip-1 framing this block performs framing for receive and transmit according to the selected iso mode and bit rate settings. in reception it takes the demodulated sub-carrier signal from the receiver. it recognizes the sof, eof and data bits, performs parity and crc check, organizes the received data in bytes and places them in the fifo. during transmit, it operates inversely, it ta kes bytes from the fifo, generates parity and crc bits, adds sof and eof and performs final encoding before passing the modulation signal to the transmitter. in transparent mode, the framing and fifo ar e bypassed, the digitized sub-carrier signal (the receiver output), is directly sent to th e sdatao pin, and the signal applied to the sdatai pin is directly used to modulate the transmitter. 1.1.10 fifo the ST25R3910 contains a 32-byte fifo. dependi ng on the mode, it contains either data that has been received or data to be transmitted. 1.1.11 control logic the control logic contains i/o registers that defi ne operation of device. 1.1.12 spi a 4-wire serial peripheral interface (spi) is used for communication between the external microcontroller and the ST25R3910. functional overview ST25R3910 10/65 docid029768 rev 2 1.2 application information the minimum configurations required to operate the ST25R3910 are shown in figure 2 and figure 3 . figure 2. minimum configuratio n with single sided antenna dr iving (including emc filter) 0 6 9 6 7 5 9 ' ' ( 1 6 ( 1 6 ' $ 7 $ 2 6 ' $ 7 $ , 6 & / . 0 & 8 b & / . 5 ) 5 ) 5 ) , 5 ) , 0 & 8 9 7 5 , 0 b [ 7 5 , 0 b [ $ * ' 9 6 6 9 6 3 b $ 9 6 3 b 5 ) 9 6 1 b 5 ) 9 6 1 b $ ; 7 , ; 7 2 9 6 1 b ' $ q w h q q d f r l o , 1 7 5 7 ( 6 7 docid029768 rev 2 11/65 ST25R3910 functional overview 35 figure 3. minimum configurati on with differential antenna driving (including emc filter) 1.2.1 operating modes the ST25R3910 operating mode is de fined by the contents of the operation control register . at power-up all bits of the operation control register are set to 0, the ST25R3910 is in power-down mode. in this mode afe static po wer consumption is minimized, only the por and part of the bias are active, while the regulators are transparent and are not operating. the spi is still functional in this mode so all settings of iso mode definition and configuration registers can be done. control bit en (bit 7 of the operation control register ) is controlling the quartz crystal oscillator and regulators. when this bit is set, the device enters in ready mode. in this mode the quartz crystal oscilla tor and regulators are enabled. an interrupt is sent to inform the microcontroller when the oscillator frequency is stable. enable of receiver and transmitter are separated so it is possible to operate one without switching on the other (control bits rx_en and tx_en). in some cases this may be useful, if the reader field has to be maintained and there is no tag response expected, the receiver can be switched-off to save current. another example is the nfcip- 1 active communication receive mode in which the rf field is genera ted by the initiator and only the receiver operates. the receiver also has a low power mode in which its power consumption (and then its sensitivity) is reduced. this mode is entered in by setting control bit rx_lp. the last control bit of the operation control register is nfc_t bit. setting of this bit is only allowed in case the nfc mode is set in the iso mode definit ion register. setting this bit to one, while all other bits are set to 0, puts the ST25R3910 into initia l nfc target mode. in 0 6 9 6 7 5 9 ' ' ( 1 6 ( 1 6 ' $ 7 $ 2 6 ' $ 7 $ , 6 & / . 0 & 8 b & / . 5 ) 5 ) 5 ) , 5 ) , 0 & 8 9 7 5 , 0 b [ 7 5 , 0 b [ $ * ' 9 6 6 9 6 3 b $ 9 6 3 b 5 ) 9 6 1 b 5 ) 9 6 1 b $ ; 7 , ; 7 2 9 6 1 b ' $ q w h q q d f r l o , 1 7 5 7 ( 6 7 functional overview ST25R3910 12/65 docid029768 rev 2 this low power mode, only the target activa tion detector, which will de tect a presence of external rf field, is active. once the presence of external rf field is detected, an interrupt is sent to the microcontroller, wh ich will in turn switch on t he oscillator and the receiver. 1.2.2 transmitter the transmitter contains two identical push-pull driver blocks connected to the pins rfo1 and rfo2. each driver is composed of eight segments having binary weighted output resistance. the msb segment ty pical on resistance is 3 ? , when all segments are turned on; the output resistance is typically 1.5 ? . all segments are turned on to define the normal transmission (non-modulated) level. it is also possible to switch off certain segments when driving the non-modulated level to reduce the am plitude of the signal on the antenna and/or to reduce the antenna q factor without making any hardware changes. am modulation and operation of the driver s egments is controlled by writing am modulation depth and antenna driver registers. antenna driver non-modulated level definition register defines which segments will be used to define normal, non- modulated level. modulation depth definition register and antenna driver am modulated level definition register are used to define how the am modulated level is set-up. it can be set-up automatically by definition of modulation depth and the direct command calibrate modulation depth or by a direct definition of segments which are turned off during am modulation. 1.2.3 receiver the receiver performs demodulation of the tag sub-carrier modulation that is superimposed on the 13.56 mhz carrier frequency. it performs am and/or pm demodulation, amplification, band-pass filtering and digitalization of sub-carrier signals (848, 424 and 212 khz subcarrier frequencies are supported). additionally it performs rssi measurement, automatic gain control (agc) and squelch. the receiver is switched on when operation control register bit rx_en is set. the operation of the receiver is additionally controlled by t he signal rx_on, set high when modulated signal is expected on the receiver input. this is automatically done after every transmit command. signal rx_on can be also forced high by sending direct command unmask receive data. signal rx_on is used to contro l features like rssi and agc. am demodulation is performed using a peak fo llower. both the positive and negative peaks are tracked to suppress common mode signal. in case external demodulation is carried out the peak follower stage can be bypassed by setting bit envi in configuration register 2 . in case of pm demodulation signal coming from the phase detector is replacing the output of peak follower. next stage in signal processing is the buffer amplifier followed by second order low pass filter with adjustable corner frequency. final stage is a first order high pass filter with adjustable corner frequency. the digital signal representing tag subcarrier modulation is produced by a window comparator. filter setting is done automatically when iso mode and data rate are chosen by writing iso mode definition register . setting is displayed in the receiver configuration register and can be changed by rewriting this register. in transparent mode the iso mode definition register is not used and filter selection has to be done by writing receiver configuration register . by setting the operation control register bit rx_lp receiver operates in low power mode. in this mode, power cons umption is lower but receiver sensitivity is reduced (see section 3: electrical characteristics on page 58 ). docid029768 rev 2 13/65 ST25R3910 functional overview 35 gain reduction, agc and squelch the total gain of receiver chain is 160. in certai n conditions it is desirable to reduce this gain. there are several features implemented in the receiver to reduce this gain. automatic gain reduction (agc) the automatic gain control feature is useful in case the tag is close to the reader. in such conditions the receiver chain is in saturation and demodulation can be influenced by system noise and saturation of last gain stage. when agc is switched on receiver gain is reduced so that the input to digitizer stage is not saturated. the agc syst em comprises a window comparator with a window three times larger than the one of the digitalization window comparator. when the agc function is enabled the gain is reduced until there are no transitions on its output. such procedure ensu res that the input to digitalization window comparator is less than three times larger than its window. agc operation is controlled by the receiver configuration register bits agc_en and agc_m. agc_en bit enables agc operation, agc_m def ines agc operating mode. the agc action is started 20 s after the rising edge of signal rx_on. in case agc_m bit is 0 it will operate during a complete receive period, in case it is 1 it will operate on the first 8 subcarrier pulses. the agc is reducing gain by 21 db in 7 steps of 3 db. when signal rx_on is low agc is in reset. squelch this feature is designed for operation of th e receiver in noisy conditions. the noise can come from tags (caused by the processing of reader commands), or it can come from a noisy environment. this noise may be misinterpreted as start of tag response, resulting in decoding errors. during execution of the squelch procedure th e output of the digitizing comparator is observed. in case there are more than two transitions on this output in a 50 s time period, the receiver gain is reduced by 3 db, and t he output is observed during the next 50 s. this procedure is repeated until the number of transitions in 50 s is lower or equal to two, or until the maximum gain reduction is reached. this gain reduction can be cleared sending the direct command clear squelch. during execution of the direct command squelc h the digital output of receiver (output of window comparator mentioned above) is observed. in case there are more than two transitions on this output in 50 s time period, the gain is reduced by 3 db and output is observed during next 50 s. this procedure is repeated until the number of transitions in 50 s is lower or equal to two, or until the maxi mum gain reduction (21 db) is reached. this setting is cleared with direct command clear squelch. setting gain reduction by setting bits rg2 to rg0 in receiver configuration register receiver gain can also be reduced in seven steps of 3 db. actual gain reduction is comb ination of all three gain reduction features mentioned above (agc, squelch and setting gain reduction in receiver configuration register ). actual gain reduction state can also be observed by reading the receiver state display register bits gr_2 to gr_0. functional overview ST25R3910 14/65 docid029768 rev 2 rssi the receiver also performs the rssi (receive d signal strength indicator) measurement of the modulated signal that is superimpos ed on the 13.56 mhz carrier. the rssi measurement is started after the rising edge of rx _on. it stays active as long as signal rx_on is high, it is frozen while rx_on is low. th e rssi is a peak hold system, and the value can only increase from the initia l zero value. every time the agc reduces the gain the rssi measurement is reset and starts from zero. re sult of rssi measurements is a 4-bit value that can be observed by reading the receiver state display register . the lsb step is 2.15 db. since the rssi measurement is of peak hold type the rssi measurement result does not follow any variations in the sign al strength (the highest value will be kept). in order to follow rssi variations it is possible to reset the rssi bits and restart the measurement by sending the direct command clear rssi. 1.2.4 a/d converter the ST25R3910 contains an 8-bit successive approximation a/d converter. inputs to the a/d converter can be multiplexed from differ ent sources to be used in several direct commands and adjustment procedures. the result of the last a/d conversion is stored in the a/d output register . the a/d converter has two operati ng modes, absolute and relative. ? in absolute mode the low reference is 0 v and the high reference is 2 v. this means that a/d converter input range is from 0 to 2 v, 00h code means input is 0 v or lower, ffh means that input is 2 v - 1 lsb or higher (lsb is 7.8125 mv). ? in relative mode low reference is 1/6 of v sp_a and high reference is 5/6 of v sp_a , so the input range is from 1/6 to 5/6 v sp_a . relative mode is only used in phase measurem ent (phase detector output is proportional to power supply). in all other cases absolute mode is used. the a/d converter input can also be access ed externally. when the direct command ad convert is sent, an a/d conversion of voltage present on pin ad_in is performed in absolute mode, result is stored in a/d output register . ad_in pin should be left non-connected in case a/d conversion is not needed in application. 1.2.5 phase and am plitude detector phase detector the phase detector is observing phase differ ence between the transmitter output signals (rfo1 and rfo2) and the receiver input signals rfi1 and rfi2, which are proportional to the signal on the antenna lc tank. these signals are first elaborated by digitizing comparators, then digitized signals are processed by a phase detector. filter characteristics of the phase antenna are adapted to one of the two possible operation modes. for antenna tuning check, a strong low power filter is used to get average phase difference, for pm demodulation a low pass filter having 1 mhz corner frequency is used to pass the subcarrier frequency. the phase detector output is inversely proporti onal to the phase difference between the two inputs. the 90 phase shift (ideal antenna lc tank tuning) results in v sp /2 output voltage. docid029768 rev 2 15/65 ST25R3910 functional overview 35 if the antenna lc tank is detuned, phase shift changes, resulting in a different phase detector output voltage. in case of co mmand check antenna resonance phase detector output is applied to a/ d co nverter in relative mode. output of phase detector is also observed by comparator with reference signal v sp /2. output of this comparator is used in execution of direct command calibrate antenna. the phase detector has low pass characteristics in case of pm demodulation. this is to enable phase demodulation of the 848 khz subcar rier signal. the output is then fed to the receiver. amplitude detector signals from pins rfi1 and rfi2 are used as in puts to the self-mixing stage. the output of this stage is a dc voltage proportional to am plitude of signal on pins rfi1 and rfi2. this signal is fed to the a/d conv erter when amplitude of signal on rfi inputs has to be measured (direct commands measure rf and calibrate modulation depth). 1.2.6 external field detector the external field detector is used in nfc mode to detect the presence of an rf field. it is composed of two sub-blocks, target activa tion detector and a rf collision avoidance detector. input to both blocks is the signal fr om the rfi1 pad. the thresholds of the two blocks can be independently set by writing the nfcip field detection threshold register . the outputs of both detectors are fed to a logi c or gate, whose output is fed to the control logic. a low to high transition of this logic or ga te output triggers an in terrupt (interrupt due to nfc event). target activation detector this block is turned on in nfc target mode to de tect the presence of an interrogator field. it is enabled by setting the operation control register bit nfc_t. it is a low power block with an adjustable threshold in the range from 145mvpp and 590mvpp. this block generates an interrupt when an external field is detecte d and also when it disappears. with such implementation it can also be used to detect th e moment when the external field disappears. this is useful to detect the moment when extern al nfc device (it can either an interrogator or a target) has stopped emitting an rf field si nce a response can only be sent afterwards. actual state of the target acti vation detector can be checked by reading the bit rfp in the receiver state display register . when this bit is set to logic one, there is a signal higher than the threshold present on the input of target activation detector. rf collision avoidance detector this block is activated during the rf collis ion avoidance sequence which is executed before every request or response in nfc active communication (initial or response rf collision avoidance). in case during the rf collision avoidance seq uence the presence of an external field is detected, request/response is not sent, an interrupt is generated to inform the external controller about collision. during rf co llision avoidance, the target activation detector is disabled in order to have the correct threshold when detection is made. the threshold of the rf collision avoidance detector can be adjusted in the range from 50 to 1080 mvpp. functional overview ST25R3910 16/65 docid029768 rev 2 1.2.7 quartz crystal oscillator the quartz crystal oscillator c an operate with 13.56 and 27.12 mhz crystals. the oscillator is based on an inverter stage supplied by cont rolled current source. a feedback loop is controlling the bias current in order to regulate amp litude on xti pin to 1 v pp . this feedback ensures reliable operation even in ca se of low quality crystals, with r s up to 50 ? . to enable a fast reader start-up an interrupt is se nt when the oscillator amplitude exceeds 750 mv pp . the oscillator block always provi des 13.56 mhz clock signal to the rest of the ic. in case of 27.12 mhz crystal clock signal is internally divided by two. divi der is controlled by configuration register 2 bit osc. division by two ensures that the 13.56 mhz signal has a duty cycle of 50%, which is better for the transmitter performance (no pw distortion). use of 27.12 mhz crystal is therefore recommended. in case of 13.56 mhz crystal, the bias current of stage which is digitizing oscillator signal is increased to minimize the pw di stortion. the oscillato r output is also used to drive a clock signal output pin, which can be used by the external microcontroller (mcu_clk). by setting configuration register 2 the frequency can be chosen between 13.56, 6.78 and 3.39 mhz. any microcontroller processing generates noi se, which may be captured by the ST25R3910 receiver. using mcu_clk as the microcontrolle r clock source generates noise synchronous with the reader carrier frequency that is filter ed out by the receiver, while using some other incoherent clock source produces noise which may generate some sideband signals captured by receiver. it is then recommended to use mcu_clk as microcontroller clock source. 1.2.8 power supply, regulators the ST25R3910 includes two regulators that ca n be adjusted automatically to improve the reader psrr. vdd is an external power supply pin, used to supply the logic and digital pins. one regulator is used to supply analog blocks (v sp_a ), another is reserved for the transmitter (v sp_rf ) in order to decouple transmitter current spikes from the rest of the ic. all negative power supply pins are externally connected to the same negative supply, the reason for separation is the need to decouple noise induced by voltage drops on the internal power supply lines. these pins are vss (die su bstrate potentia l), vsn_d (negative supply of logic and digital pads), vsn_a (negative s upply of analog blocks) and vsn_rf (negative supply of tr ansmitter). an additional regulator block provides agd vo ltage (1.5 v), which is used as reference potential for analog processing (analog ground). blocking capacitors have to be connected externally to regula tor outputs and agd pins. for pi ns vsp_a and vsp_rf recommended blocking capacitors are 2.2 f in parallel with 10 nf, for pin agd 1 f in parallel with 10 nf is suggested. the regulated voltage ranges from 2.4 to 3.4 v, with 100 mv step. both regulators are set to the same voltage. v sp_a regulator maximum capability is 20 ma while maximum capability of v sp_rf regulator is 300 ma. v sp_rf regulator also has a built-in protection limiting current to 300 ma in normal operation and to 500 ma in case of a short. the regulators are operating when either the operation control register bit en is set or pin en is high. in power-down mode the regulators are not operating, v sp_a and v sp_rf are connected to v dd through 1 k ? resistors, to ensure smooth power-up of the system and a smooth transitions from stand-by mode to other operating modes. in case regulators were regulating or were transparent at power-up a large current would be pulled from v dd supply to charge blocking capacitors of regulated ou tputs, a problematic situation for battery powered systems. docid029768 rev 2 17/65 ST25R3910 functional overview 35 at power-up the regulated voltage is set to its maximum, i.e. 3.4 v. the regulator voltage can then be set automatic ally or ?manually?. the automatic procedure is started by sending the direct command adjust regulators. in this procedure regulated voltage is set 250 mv below v dd . this procedure ensures that reader operates with maximum possible power while still achieving a good psrr. regulator operation can be controlled and obse rved by writing and reading two regulator registers. regulator display register is a read only register that displays actual regulated voltage when regulator is operating. in power-down mode its content is forced to 00. by writing regulated voltage definition register the user chooses between automatic and ?manual? adjustment of regulated voltage. au tomatic mode is chosen when bit reg_s is 0 (default and also recommended state). when bit reg_s is asserted to 1 regulated voltage is defined by bits rege_3 to rege_0 of the same register. 1.2.9 communication with an external microcontroller the ST25R3910 is a slave devices and the external microcontr oller initiates all communication. communication is performed by a 4-wire serial peripheral interface (spi). the ST25R3910 sends an interrupt request (pin intr) to the microcontroller, which can use clock signal available on pin mcu_clk when the oscillator is running . the microcontroller can also drive pin en. putting this pin high has the same function as setting the operation control register bit en (entry in ready mode). serial peripheral interface (spi) while signal sen is low the spi interface is in reset, while it is high the spi is enabled. it is recommended to keep sen low whenever the spi is not in use. sdatai is sampled at the falling edge of sclk. all communicati on is done in blocks of 8 bits (bytes). first two bits of first byte transmitted after low to high tr ansition of sen define spi operation mode. msb bit is always transmitted first (valid for address and data). read and write modes support address auto-i ncrementing. this means that if some additional data bytes are sent/read after the address and first data byte, they are written to/read from addresses incremented by ?1?. figure 4 defines possible modes. table 1. serial data interface (4-wire interface) signal lines name signal signal level description sen digital input cmos spi enable (active low) sdatai digital input serial data input sdatao digital output with tristate serial data output sclk digital input clock for serial communication functional overview ST25R3910 18/65 docid029768 rev 2 figure 4. exchange of signals with microcontroller when signal sen is low, the spi interface is in reset and sdatao is in tristate; when it is high, spi interface is enabled. it is recommend ed to keep signal sen low whenever the spi interface is not in use. sdatai is sampled at the falling edge of sclk. all communication is done in blocks of 8 bits (bytes). the first two bi ts of the first byte transmitted after low to high transition of sen define the spi operation mode. table 2 defines the possible modes. writing data to addressable registers (write mode) figure 5 and figure 6 show cases of writing a single by te and writing mu ltiple bytes with auto-incrementing address. sd atai is sampled at the fallin g edge of sclk. a sen low pulse indicates the end of the write command after register has been written. auto incrementing address is supported, this means that if after the address and first data byte some additional data bytes are sent, they are wr itten to addresses incremented by 1. if the command is terminated by putting sen low before a packet of 8 bits composing one byte is sent, writing of this register is not performed. in case the register on the defined address does not exist or it is a read only register, no write is performed. 0 6 9 , 2 6 ' $ 7 $ , 6 ' $ 7 $ 2 0 , 6 2 0 2 6 , 6 7 5 6 h s d u d w h 6 3 , l q s x w d q g r x w s x w v l j q d o v w r 0 & 8 % l g l u h f w l r q d o g d w d , 2 v l j q d o w r 0 & 8 6 7 5 6 ' $ 7 $ , 6 ' $ 7 $ 2 table 2. spi operation patterns mode mode pattern (communication bits) mode related data mode register address register data m1 m0 c5 c4 c3 c2 c1 c0 d7 d6 d5 d4 d3 d2 d1 d0 write 0 0 a5 a4 a3 a2 a1 a0 wd7 wd6 wd5 wd4 wd3 wd2 wd1 wd0 read 0 1 a5 a4 a3 a2 a1 a0 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 fifo load 1 0 0 0 0 0 0 0 wd7 wd6 wd5 wd4 wd3 wd2 wd1 wd0 fifo read 1 0 1 1 1 1 1 1 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 command11c5c4c3c2c1c0-------- docid029768 rev 2 19/65 ST25R3910 functional overview 35 figure 5. spi communication: writing a single byte figure 6. spi communication: writing multiple bytes reading data from addressable registers (read mode) the command control byte for a read command consists of a command code and an address. after the command code, the address of register to be read has to be provided from the msb to the lsb. then one or more data bytes can be transferred from the spi slave to the master, always from the msb to the lsb. as in case of write, the read command supports auto-incrementing address. to tran sfer bytes from consec utive addresses, spi master has to keep the sen signal high and the sclk has to be active as long as data need to be read from the slave. sdatai is sampled at the falling edge of sclk, data to be read from the ST25R3910 internal register is driven to sdatao pin on rising edge of sclk and is sampled by the mcu at the falling edge of sclk. 0 6 9 ' ; ; 6 ( 1 6 & / . 6 ' $ 7 $ , 7 z r o h d g l q j e l w v l q g l f d w h 0 r g h 6 & / . u l v l q j h g j h ' d w d w u d q v i h u u h g i u r p 0 & 8 6 & / . i d o o l q j h g j h ' d w d l v v d p s o h g ' d w d l v p r y h g w r d g g u h v v $ $ ! ) d o o l q j h g j h l q g l f d w h v h q g r i : u l w h 0 r g h ' ' ' ' ' ' ' $ $ $ $ $ $ 0 6 9 ) d o o l q j h g j h l q g l f d w h v h q g r i : u l w h p r g h 7 z r o h d g l q j v l q g l f d w h : u l w h p r g h 6 & / . i d o o l q j h g j h ' d w d p r y h g w r d g g u h v v $ $ ! $ $ $ $ $ $ ' ' ' ' ' ' ' ' ; ; ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' 6 ( 1 6 & / . 6 ' $ 7 $ , 6 & / . i d o o l q j h g j h ' d w d p r y h g w r d g g u h v v $ $ ! 6 & / . i d o o l q j h g j h ' d w d p r y h g w r d g g u h v v $ $ ! q 6 & / . i d o o l q j h g j h ' d w d p r y h g w r d g g u h v v $ $ ! q functional overview ST25R3910 20/65 docid029768 rev 2 a sen low pulse has to be sent after register data has been transferred in order to indicate the end of the read command and to prepare the interface to the next command control byte. in case the register on defined address does not exist all 0 data is sent to sdatao. figure 7 is an example for reading of single byte. figure 7. spi communication: reading a single byte loading transmitting data into fifo loading the transmitting data into the fifo is similar to writing data into an addressable registers. difference is that in case of loading more bytes all bytes go to the fifo. spi operation mode bits 10 indicate fifo operation s. in case of loading transmitting data into fifo all bits docid029768 rev 2 21/65 ST25R3910 functional overview 35 figure 8. spi communication: loading of fifo reading received data from fifo reading received data from the fifo is similar to reading data from an addressable registers. difference is that in case of reading more bytes th ey all come from the fifo. spi operation mode bits 10 indicate fifo operations. in case of reading the received data from the fifo all bits functional overview ST25R3910 22/65 docid029768 rev 2 direct command mode direct command mode has no arguments, so a si ngle byte is sent. spi operation mode bits 11 indicate direct command mode. the following six bits define command code, sent msb to lsb. the command is executed on falling edge of last clock (see figure 10 ). figure 10. spi communication: direct command interrupt interface when an interrupt condition is met the source of interrupt bit is set in the interrupt register and the intr pin transitions to high. the microcontroller then reads the interrupt register to distinguish between different interrupt sources. after the interrupt register is read its content is reset to 0 and intr pin signal transitions to low. note: there may be more than one interrupt bi t set in case the microcontroller does not immediately read the interrupt register after the intr signal has been set and another event causing interrupt has occurred. if an interrupt from a certain source is no t required, it can be disabled by setting corresponding bit in the mask interrupt register . when masking a given interrupt source the interrupt is not produced, but the source of interrupt bit is still set in interrupt register . after reading the interrupt register the 13.56 mhz clock coming fr om the oscillator is used to produce a reset signal that clears it and re sets intr signal. practi cally in all interrupt cases the oscillator is running when an interr upt is produced. the only exception is the interrupt in the initial nfc ta rget mode where only the target activation detector is operating. in this case the interrupt is cleared with first sclk rising edge following reading of the interrupt register (an extra dummy clk pulse during reading of the interrupt register or the first sclk pulse of the next spi command will do the job). 0 6 9 6 & / . u l v l q j h g j h ' d w d l v w u d q v i h u u h g i u r p 0 & 8 6 & / . i d o o l q j h g j h ' d w d l v v d p s o h g 6 & / . i d o o l q j h g j h l q g l f d w h v v w d u w r i f r p p d q g h [ h f x w l r q 7 z r o h d g l q j v l q g l f d w h & r p p d q g 0 r g h & ; ; 6 ( 1 6 & / . 6 ' $ 7 $ , & & & & & table 3. intr output name signal signal level description intr digital output cmos interrupt output pin docid029768 rev 2 23/65 ST25R3910 functional overview 35 fifo water level and fifo status registers the ST25R3910 contains a 32 byte fifo. in case of transmitting the control logic shifts the data that was previously loaded by the exte rnal microcontroller to the framing block and further to the transmitter. during reception, the demodulated data is stored in the fifo and the external microcontroller can download received data at a later moment. transmit and receive capabilities of the st25r3 910 are not limited by the fifo size due to a fifo water level interrupt system. during transmission an interrupt is sent ( intr due to fifo water level in the interrupt register ) when the content of data in the fifo still to be sent is lower than th e fifo water level for receive. the external microcontroller can now add more data in the fifo. the same stands for the reception: when the number of received bytes exceeds th e fifo water level for receive an interrupt is sent to inform the external controller that data has to be downloaded from fifo. the external controller has to serve the fifo faster than data is transmitted or received. using sclk frequency that is at least double th an the actual receive or transmit bit rate is recommended. there are two settings of the fifo water leve l available for receive and transmit in the configuration register 5 . after data are received the external microcontroller needs to know how long the received data string was before downloading data from the fifo: this information is available in the fifo status register , which displays number of bytes in the fifo that were not read out. the fifo status register also contains a fifo overflow bi t, set when during reception the external processor did not react on time and more than 32 bytes were written in fifo (the received data are lo st in this case). 1.2.10 direct commands table 4. direct commands code command comments 000001 set default puts the ST25R3910 in default state (same as after power-up) 000010 clear stops all activities and clears fifo 000100 transmit with crc starts a transmit sequence using automatic crc generation 000101 transmit without crc starts a transmit seque nce without automatic crc generation 000110 transmit reqa transmits reqa command (iso-14443a mode only 000111 transmit wupa transmits wupa command (iso-14443a mode only) 001000 nfc transmit with initial rf collision avoidance equivalent to transmit with crc with additional rf collision avoidance 001001 nfc transmit with response rf collision avoidance 001010 nfc transmit with response rf collision avoidance with n=0 010000 mask receive data receive after this command is ignored functional overview ST25R3910 24/65 docid029768 rev 2 set default this direct command puts the ST25R3910 in the same state as power-up initialization. all registers are initialized to the default state. note: results of different calibration and adjust commands are also lost. this direct command is accepted in all operating modes. clear this direct command stops all current activities (transmission or reception) and clears fifo. it also clears collision and interrupt registers. this command has to be sent first in a sequence preparing a transmission (except in case of direct commands transmit reqa and transmit wupa). transmit commands all transmit commands (transmit with crc, transmit without crc, transmit reqa and transmit wupa) are accepted only in case the transmitter is enabled (bit tx_en is set). 010001 unmask receive data received data following this command are normally processed (this command has priority over internal mask receive timer) 010010 ad convert a/d conversion of signal on ad_in pin is performed, result is stored in a/d output register 010011 measure rf rf amplitude is measured, result is stored in a/d output register 010100 squelch performs gain reduction based on the current noise level. 010101 clear squelch resumes gain settings in place before sending squelch command 010110 adjust regulators adjusts supply regulators according to the current supply voltage level 010111 calibrate modulation depth starts sequence which activa tes the tx, measures the modulation depth and adapts it to comply with the specified modulation depth 011000 calibrate antenna starts the sequence to adjust parallel capacitances connected to trimx_y pins so that the antenna lc is in resonance. 011001 check antenna resonance measurement of antenna lc tank resonance to determine whether calibration is needed. 011010 clear rssi clears rssi bits and restarts the measurement 011100 transparent mode enters in transparent mode table 4. direct commands (continued) code command comments docid029768 rev 2 25/65 ST25R3910 functional overview 35 nfc transmit commands the nfc transmit commands (nfc transmit with initial rf collis ion avoidance, nfc transmit with re sponse rf collision avoidance, nfc transmit with response rf collision avoidance with n=0) are used to transmit requ ests and responses in the nfc mode. before actual transmission th e rf collision avoidance with collisio n avoidance threshold defined in the nfcip field detection threshold register is performed. in the command nfc transmit with response rf collision avoidance n is randomly set in a range from 0 to 3, while in the command nfc transmit with response rf collision avoidance with n=0 it is set to 0. in case collision is de tected during the rf collision avoidance the transmission is not done and an inte rrupt is sent with flag intr due to nfc event. the nfc transmit commands switch on and off the transmission block, setting the operation control register bit tx_en in the nfc mode is not allowed. timing of the nfc transmit commands (see table 5 ) is according to the iso/iec 18092 standard, which specifies a range for some of them. t an interrupt due to end of transmission is sent when rf field is switched off. all nfc transmit commands are on ly authorized in case the iso mode configuration bit nfc is set and the oscillator and regulators are running. mask receive data and unmask receive data after the direct command mask receive data the signal rx_on that enables the rssi and agc operation of the receiver (see section 1.1.2: receiver ) is forced to low, processing of the receiver output by the receive data framing block is disabled. this command is useful to mask receiver and receive framing from processing the data when there is actually no input and only a noise would be processed.. the direct command unmask receive data is enabling normal processing of the received data (signal rx_on is set high to enable the rssi and agc operation), the receive data framing block is enabled. a common use of this command is to enable again the receiver operation after it was masked by the command mask receive data. the command unmask receive data has to be used in the nfc target mode. the sequence implemented in the ST25R3910 supp oses that every action is started with a transmit command, after sending the transmit data, the receive mode is automatically entered to process the respon se. such a sequence is always in place in case of the table 5. nfc p2p timings implemented in ST25R3910 symbol parameter value unit comments t idt initial delay time 302 s initial rf collision avoidance t rwf rf waiting time 37.76 - t irfg initial guard time 5.11 ms initial rf collision avoidance t adt active delay time 151 s response rf collision avoidance t arfg active guard time 84 t gas guard time after sending response or request 65 time during which rf fi eld stays switched on after sending a response or a request. not specified in the iso/iec 18092. functional overview ST25R3910 26/65 docid029768 rev 2 iso-14443 reader mode and in the nfcip mode, where the ST25R3910 is the initiator. in case of nfc target mode this sequence is st arted by receiving the interrogator request. after the interrupt caused by the first initiator request command unmask receive data is sent to force the ST25R3910 in receive mode. the commands mask receive data and unmask receive data are only accepted when the receiver is enabled (bit rx_en is set). ad convert a/d conversion of signal on ad_in pin is performed; result is stored in a/d output register (see section 1.1.4 on page 8 ). duration time: 42 s max. this command is accepted in any mode where the oscillato r and regulators are running. measure rf this command measures the amplitude on the rfi inputs and stores result in the a/d output register (see also section 1.1.4 on page 8 and section 1.1.3 on page 8 ). when this command is executed the output of the amplitude detector is multiplexed to the a/d converter input (the a/d converter is in absolute mode). the amplitude detector conversion gain is 0.6 v inpp /v out . one lsb of the a/d converter output represents 13.02 mv pp on the rfi inputs, a 3 v pp signal (the maximum allowed level on each of the two rfi inputs) results in 1.8 v output dc volta ge and produces the value 1110 0110 on the a/d converter output. duration time: 42 s max. this command is accepted in any mode where the oscillato r and regulators are running. squelch this direct command is intended to avoid demodu lation problems of tags that produce a lot of noise during data processing. it can also be used in a noisy environment. the operation of this command is explained in squelch . duration time: 500 s max. this command is only accepted when the transmitter and the receiver are operating. clear squelch clears the gain reduction that was set by sending squelch command. this command is accepted in any mode. adjust regulators when this command is sent the power supply level of v dd is measured in maximum load conditions and the regulated voltage reference is set 250 mv below this measured level to ensure maximum possible stable regulated supply (see section 1.2.8: power supply, regulators ). the use of this command increases the system pssr. at the beginning of executio n of the command, both the receiver and transmitter are switched on to have the maximum current consumption, and the regulators are set to their maximum regulated voltage (5.1 v in case of 5 v supply and 3.4 v in case of 3.3 v supply). after 300 s v sp_rf is compared to v dd , if is not at least 250 mv lower the regulator setting docid029768 rev 2 27/65 ST25R3910 functional overview 35 is reduced by one step (120 mv in case of 5 v supply and 100 mv in case of 3.3 v supply) and measurement is done after another 300 s. the procedure is repeated until v sp_rf drops at least 250 mv below v dd , or until the minimum regulated voltage (3.9 v in case of 5 v supply and 2.4 v in case of 3.3 v supply) is reached. duration time: 5 ms max. this command is accepted in any mode wh ere the oscillator and regulators are running. this command is not accepted when the external definition of the regulated voltage is selected in the regulated voltage definition register (bit reg_s is set to h). calibrate modulation depth starts a sequence that activates the transmission, measures the modulation depth and adapts it to comply with the mo dulation depth specified in the modulation depth definition register . the result of the calibration procedure is stored in the modulation depth display register . refer to section 1.2.14: am modulation dept h: definition and calibration for details about setting the am modulation depth and running this command. duration time: 10 ms max. this command is accepted in any mode wh ere the oscillator and regulators are running. calibrate antenna sending this command starts a sequence that adjusts the parallel capacitances connected to trimx_y pins so that the antenna lc tank is in resonance. see section 1.2.15: antenna tuning for details. duration time: 400 s max. this command is accepted in any mode wh ere the oscillator and regulators are running. check antenna resonance this command measures the antenna lc tank resonance to determine whether a calibration is needed. see check antenna resonance for details. duration time: 42 s max. this command is accepted in any mode where the oscillato r and regulators are running. clear rssi the receiver automatically clears the rssi bits in the receiver state display register and starts to measure the rssi of the received signal when the signal rx _on is asserted. since the rssi bits store peak value (peak-hold type) the variations of the receiver input signal will not be followed (this may happen in case of long messages or test procedures). the direct command clear rssi clears the rssi bits in the receiver state display register , and the rssi measurement is restarted (in ca se, of course, rx_on is still high). transparent mode enters in the transparent mode. the transpar ent mode is entered on the falling edge of signal sen and is maintained as long as signal sen is kept low. this command is accepted only when the transmitter and the receiver are operating. functional overview ST25R3910 28/65 docid029768 rev 2 1.2.11 operating sequence at power-up, the ST25R3910 enters the power-do wn mode. the content of all registers is set to the default state. 1. the microcontroller, after a power-up, should load the iso mode definition register and the configuration registers to configure reader operation. 2. configure the regulators. it is recommended to use direct command adjust regulators to improve the system psrr. 3. when implementing the lc tank tuning, send the direct command calibrate antenna. 4. when using the am modulation (iso-14443b for example), set the modulation depth in the am modulation depth control register and send the command calibrate modulation depth. 5. the ST25R3910 is now ready to operate. 1.2.12 iso-14443 reader operation to begin with, the ready mode has to be entered by setting the en bit of the operation control register or by asserting pin en. in this mo de the oscillator is started and the regulators are enabled. when the oscillator operation is stable an interrupt is sent. before sending any command to a tag, the transmitter and receiver have to be enabled by setting the bits rx_en and tx_en. if reqa or wupa have to be sent, this is simply done by sending the appropriate direct command, otherwise the following sequence has to be followed: 1. send the direct command clear 2. define the number of transmitted bytes in the number of transmitted bytes register 0 and number of transmitted bytes register 1 3. write the bytes to be transmitted in the fifo 4. send the direct command transmit with crc or transmit withou t crc (whichever is appropriate) 5. when all the data is transmitted an interrup t is sent to inform the microcontroller that the transmission is finished (i ntr due to end of transmission) after the transmission is executed, the ST25R3910 receiver automatically starts to observe the rfi inputs to detect a tag response. the rssi and agc (when enabled) start. the framing block processes the sub- carrier signal from receiver a nd fills the fifo with data. when the reception is finished and all the data is in the fifo an inte rrupt is sent to the microcontroller (intr due to end of receive), additionally the fifo status register displays the number of bytes in the fifo so that the microcontroller can proceed with data download. in case of an error or bit co llision detected during reception, an interr upt with appropriate flag is sent. transmit and receive when the data packet is longer than fifo in case a data packet is longer than fifo the sequence explained above is modified. before transmit the fifo is filled. during transm it an interrupt is sent when remaining number of bytes is lower th an the water level (irq due to fifo water level). the microcontroller in turn adds more data in th e fifo. when all the da ta is transmitted an interrupt is sent to inform the microc ontroller that transmission is finished. docid029768 rev 2 29/65 ST25R3910 functional overview 35 during reception situation is similar. in case the fifo is loaded with more data than the receive water level, an interrupt is sent and the microcontr oller in turn read s the data from the fifo. when reception is finished an interrupt is sent to the microcontroller (intr due to end of receive), additionally the fifo status register displays the number of bytes in the fifo that are still to be read out. 1.2.13 nfcip-1 operation the ST25R3910 supports only nfcip-1 106 kbit/s active mode. for operation in this mode, the bit nfc has to be set in the iso mode definition register . next, the nfcip field detection threshold register has to be written to define the thresholds for target activation and rf collision avoidance (see section 1.1.5: external field detector on page 8 ). note: in the nfc mode the transmitter enable bit (tx_en) is never set in the operation control register . the transmitter is activated automa tically by the nfc transmit commands. nfcip target the ST25R3910 enters in the initial nfc tar get mode by setting the nfc_t bit in the operation control register . in this low power mode only the target activation detector is running. when presence of an external the rf field is detected an interrupt is sent (intr due to nfc event). the microcontroller can now activate the oscillator, regulators and receiver. as explained in target activation detector , the target activation dete ctor may also be used to detect the moment when initiator turns off its rf field. if the delay time after which the initiator turns off its field afte r sending its request is known, this feature is not needed and the target activation detector can be turned of f by setting bit nfc_t low after presence of the initiator field is detected. at this point direct command unmask receive data has to be sent to put the receiver and control logic in the receive mode. the st25r391 0 is now ready to receive request from the initiator. procedure during the reception is the same as in case of the iso-14443 mode. the target response is done in the same way as in case of the is o-14443 transmission, only that the command which actually starts the transmission is either nfc transmit with response rf collision avoidance or nfc tran smit with response rf collision avoidance with n=0. these two commands perform the rf collision av oidance procedure before actually starting the transmission. in case an external rf field is detected during the rf collision avoidance proc edure an interr upt is sent (intr due to nfc event) and the transmission is not performed. at this point the ST25R3910 is waiting for a new request from the initiator. in case the target activation detector is still enabl ed an interrupt will be generate d when the initiator switch on its field. this is additional information for the external controller, but it is not required by the receiver. the receiver is al ready running, rece ption will be done automatically and an in terrupt will be sent when reception will be completed (or when the fifo water level will be reached in case of a long request). functional overview ST25R3910 30/65 docid029768 rev 2 nfcip initiator if the ST25R3910 is an nfcip init iator, the microcontroller ac tivates the oscillator and the receiver, and prepares everything for transmitting as in case of the iso-14443 transmission. the transmission is actually executed by direct command nfc tr ansmit with initial rf collision avoidance. the events that follow are the same as described in nfcip target , with the difference that the roles of the initiator and target are interchanged. the target activation detector may also be used in case of the nfcip initiator operation to detect the moment when the targ et rf field turns on and off. 1.2.14 am modulation depth: definition and calibration the am modulation of the transmitted carrier is used for communication reader to tag in two configuration cases: ? iso-14443b mode is configured in the iso mode definition register ? transparent mode with am modulation (direct command transparent mode, bit am of the configuration register 5 is set to 1) in other cases the ook modulation is used. the am modulation depth can be automatically adjusted by setting the modulation depth definition register and sending the direct command calibrate modulation depth. there is also an alternative possibility where the comm and calibrate modulation depth is not used and the modulated level is defined by writing the antenna driver am modulated level definition register . am modulation depth definition using the direct command calibrate modulation depth before sending the direct command calibrate modulation depth the modulation depth definition register has to be configured in the following way: ? bit 7 (am_s) has to be set to 0 to choose definition by the command calibrate modulation depth ? bits 6 to 1 (mod5 to mod0) define target am modulation depth definition of modulation depth using bits mod5 to mod0 the rfid standard documents usually define the am modulation level in form of the modulation index. the modulation index is defined as (a-b)/(a+b), where a and b are, respectively, the amplitude of the non-modulated carrier and of the modulated carrier. the bits mod5 to mod0 are used to calculate th e amplitude of the modulated level. the non- modulated level that was before measured by the a/d converter and stored in an 8 bit register is divided by a binary number in rang e from 1 to 1.98. bits mod5 to mod0 define binary decimals of this number. example in case of the modulation index 10% the modulated level amplitude is 1.2222 times lower than the non-modulated level. 1.2222 converted to binary and truncated to 6 decimals is 1.001110. so in order to define the modulation index 10% the bits mod5 to mod0 have to be set to 001110. docid029768 rev 2 31/65 ST25R3910 functional overview 35 table 6 shows setting of the mod bits for some often used modulation indexes. execution of direct command calibrate modulation depth the modulation level is adjusted by increasing the rfo1 and rfo2 driver output resistance. the rfo drivers are composed of 8 binary weighted segments. usually all these segments are turned on to defi ne the normal, non-modulated leve l, there is also a possibility to increase the output resistance of the non-modulated state by writing the antenna driver non-modulated level definition register . before sending the direct command calibrate modulation depth the oscillator and regulators have to be turned on. when the direct command calibrate modulation depth is sent the following procedure is executed: 1. the transmitter is turned on, non-modulated level is established. 2. the amplitude of the non-modulated carrier level established on the inputs rfi1 and rfi2 is measured by the a/d converter and stored. 3. based on the measurement of the non-modulated level and the target modulated level defined by the bits mod5 to mod0 the target modulated level is calculated. 4. the output driver control is taken over by an internal register with initial level defined in the antenna driver non-modulated level definition register . content of the internal register is incremented by 1 to increase the driver resistance and thereby reduce the carrier level. the reduced carr ier level, in turn, is measur ed by the a/d converter and compared with the target modulation level. 5. the procedure from previous point is repeated as long as the measured level is higher than the target modulation level. 6. when the measured carrier level is equal to or lower than the target modulation level, the state of the internal register is copied into the modulation depth display register , whose content is used to define the am modulated level. note: after the calibration procedure is finished, the content of the antenna driver non-modulated level definition register should not be changed. modification s of the content of this register will change the non-modula ted amplitude and therefore th e ratio between the modulated and non-modulated level. note: in case the calibration of antenna resona nt frequency in used, the command calibrate antenna has to be run before am modulation depth adjustment. table 6. setting mod bits modulation index (%) a/b (dec) a/b (bin) mod5 ? mod0 8 1.1739 1.001011 001011 10 1.2222 1.001110 001110 14 1.3256 1.010100 010100 20 1.5000 1.100000 100000 30 1.8571 1.110111 110111 33 1.9843 1.111111 111111 functional overview ST25R3910 32/65 docid029768 rev 2 am modulation depth definition using the antenna driver am modulated level definition register when bit 7 (am_s) of the modulation depth definition register is set to 1 the am modulated level is controlled by writing the antenna driver non-modulated level definition register . if the setting of the modulated level is already kn own it is not necessary to run the calibration procedure, the modulated level can be def ined just by writing this register. it is also possible to implement calibration procedure through an external controller using the antenna driver non-modulated level definition register and the direct command measure rf. the procedure is the following: 1. write the non-modulated level in the antenna driver non-modulated level definition register (usually it is all 0 to have the lower possible output resistance). 2. switch on the transmitter. 3. after the setting time, send the direct command measure rf. read result from the a/d output register . 4. calculate the target modulated level from th e target modulation index and result of the previous point. 5. in the following iterations content of the antenna driver non-modulated level definition register is modified, the command measure rf executed and the result compared with the target modulated level as long as the resu lt is not equal (or as close as possible) to the target modulated level. 6. at the end the content of the antenna driver non-modulated level definition register that results in the target modu lated level is written in the antenna driver am modulated level definition register while the antenna driver non-modulated level definition register is restored with the non-modulated definition value. 1.2.15 antenna tuning the ST25R3910 integrates the blocks needed to check and to adjust the antenna lc tank resonance frequency. the key block in the resonance frequency checking and adjustment is the phase detector , which measures the phase shift between the transmitter output signals (rfo1 and rfo2) and the inputs rfi1 and rfi2 (proportional to the voltage on the antenna lc tank). in case of perfect tuning there is a 90o phase shift between them. check antenna resonance in case of the perfect 90o phase shift mentioned above, the phase detector output results in v sp /2 output voltage. a phase shift of 1% of the carrier frequency period (3.6o) results in the output voltage change of 2% of v sp (1% phase shift results in 60mv change at v sp = 3 v). during execution of the direct command ch eck antenna resonance the phase detector output is multiplexed on the input of a/ d converter which is se t in relative mode. 1 lsb of the a/d conversion output represents 0.13% of carrier frequency period (0.468o). the result of a/d conversion is in case of the perfect tuning exactly in the middle of range (1000 0000 or 0111 1111). values higher than 1000 0000 mean that phase detector output voltage is higher than v sp /2, which correspond to resonance frequency higher than target 13.56 mhz. in the docid029768 rev 2 33/65 ST25R3910 functional overview 35 opposite case, when the resonance frequency is lower than target , the result of a/d conversion is lower than 0111 1111. execution of the command check antenna resonan ce is fast and can be used frequently to check whether system settings are correct. calibrate antenna resonance in order to implement the antenna lc tank calib ration binary weighted trimming capacitors have to be connected between the two coil terminals to the pads trim1_3 to trim1_0 and trim2_3 to trim2_0. in case single driver is used only the pads trim1_3 to trim1_0 are used, pads trim2_3 to trim2_0 are left open. figure 11 shows connection of the trim capacitors for both single (left side) and differential (right side) driving. the trimx_y pads c ontain the hvnmos switch transistors to v ss . during trimming procedure the resonance frequency is adjusted by connecting some of the trimming capacitors to v ss and leaving the other ones floating. figure 11. connection of trimming capacitors to the antenna lc tank the switches of the same binary weight are driven from the same source and are both on or off (the switches trim1_2 and trim2_2 are for example both either on of off). the breakdown voltage of the hvnmnos switch tran sistors is 30 v, th is limits the maximum peak to peak voltage on lc tank in case trimming is used. the on resistance of trim1_0 and trim2_0 switch transistors (to be connecte d to lsb trimming capacitor) is typically 50 ? at v sp = 3 v, the on resistance of other pads is binary weighted (the on resistance of trim1_3 and trim2_3 is 6.25 ? ). 0 6 9 7 5 , 0 b 7 5 , 0 b 7 5 , 0 b 7 5 , 0 b 5 ) 5 ) 5 ) , 5 ) , 7 5 , 0 b 7 5 , 0 b 7 5 , 0 b 7 5 , 0 b $ q w h q q d 7 5 , 0 b 7 5 , 0 b 7 5 , 0 b 7 5 , 0 b 5 ) 5 ) 5 ) , 5 ) , 7 5 , 0 b 7 5 , 0 b 7 5 , 0 b 7 5 , 0 b $ q w h q q d $ q w h q q d functional overview ST25R3910 34/65 docid029768 rev 2 antenna calibration using command calibrate antenna the calibration of lc tank resonance frequency is automatically done by running the direct command calibrate antenna. during executio n of this command the comparator at the output of phase detector is us ed. in case the lc tank resonance frequency is higher than the target 13.56 mhz, the phase dete ctor output gets higher than v sp /2 and the comparator output is high. in the opposite case, when the resonance frequency is lower, the phase detector output gets lower than v sp /2 and the comparator output is low. at the beginning of the command calibrate ante nna execution the switches in all trimx_y pads are turned off. as a consequence, all the trimming capacitors are disconnected so in case the lc tank dimensioning is correct the resonance frequency has to be higher than the target and the comparator output has to be high. in case the comparator output is low at this initial state the resonance frequency is too low even when all the trimming capacitor are disconnected, and adjustments of the resonance frequency are not possible. an error flag is set and execution of the command is terminated. in case the comparator output was high at the initial state, the lsb switches (trim1_0 and trim2_0) are switched on and after 10 s state of the comparator output is checked again. this procedure is repeated until the comparator output transitions to low, or until the final state with all switches turned on is reached. the switch state at which the comparator output is transitional is the one at which the lc tank is in resonance. in case the state with all switched turned on is reached while the comparator output is still high, the resonance frequency is too high ev en when all the capacitors are connected and adjustments are not possible. the error flag is set. the result of the direct command calibrate antenna can be observed by reading the antenna calibration register , which displays the state of four bits representing the state of the switches when the resonance was reached and the error flag. after the execution of the direct command ca librate antenna the resonance can be checked by running the direct command check antenna resonance. antenna calibration using external trim register there is also a possibility to control the pos ition of the trim switches by writing the external trim register . when bit trim_s is set to 1 position of the trim switches is controlled by bits tre_3 to tre_0. using this register and th e direct command check antenna resonance an external trimming procedure can be implemented. another possible external trimming procedure is to use this register and the direct command measure rf. in this case the resonance is ad justed by looking for operating point with the maximum amplitude. transparent mode the as3909/10 framing supports the iso-14443 standard. other standards as well as custom 13.56 mh z rfid reader protocols can be implemented by using the ST25R3910 afe and framing implemented in the external microcontroller. after sending the direct command transparent mode the external microcontroller directly controls the transmission modulator and gets the receiver output (the control logic becomes ?transparent?). the transparent mode is ente red on falling edge of signal sen after sending the command transparent mode and is maintained as long as the signal sen is kept low. before sending docid029768 rev 2 35/65 ST25R3910 functional overview 35 the direct command transparent mode the transmitter and receiver have to be turned on, and the afe has to be configured properly. while the ST25R3910 is in the transparent mode the afe is controlled directly through the spi interface: ? the transmitter modulation is controlled by pin sdatai (high is modulator on) ? signal rx_on is controlled by pin sclk (high enables rssi and agc) ? the receiver output is sent to pin sdatao by controlling the rx_on advanced receiver features like the rssi and agc can be used. configuration bits related to the iso mo de, framing and fifo are meaningless in transparent mode, but all other configuration bits are respected. the transmitter modulation type used (ook or am) is defined by bit am of the configuration register 5 . the direct command calibrate modulation depth supports modulation depths up to 30%, deeper am modulation is possible by writing the antenna driver am modulated level definition register . the receiver filters support the subcarrier fr equencies from 212 to 848 khz. the filter characteristics can be configured via bits fs2 to fs0 in the receiver configuration register . active receive ? use in iso-14443b anticollision in some cases it is useful to know that a response from a tag is being received. this information is provided by bit rx_act in the fifo status register . this bit is set to 1 when the start of the tag message is detected, and stays high until the end of reception. this information can be used to speed up the iso-14443b anticollision procedure when more slots are used. when there is no message in a certain slot, the reader does not have to wait for the time a complete atqb ta kes before sending the next slot-marker command, but it can send the next slot-marker as soon as it is clear that there is no answer in that particular slot. the microcontroller can obtain this info by reading the rx_act flag at the time the receiver should alread y be processing the atqb message. in case rx_act flag is set to one the receiver is processing a message and the microcontroller has to wait for the end of receiv e interrupt, in opposite case when the rx_act flag is set to zero there is no atqb message in that particular slot and the next slot-marker command can be sent immediately. iso-14443b, reduction of tr0 and tr1 and suppression of eof/sof in picc response the iso-14443-3 standar d, chapter 7.10.3 coding of param 1 defines possibility to reduce the tr0 and tr1 and suppress the eof/sof in picc response. note: the ST25R3910 receiver and framing blocks do not support the reduction of tr0 and tr1 and suppression of eof/sof. if default sett ings of these parameters are changed, the framing block will not be able to decode the picc response. test pins pins test and tio are used to test the st25 r3910. pin test is a digital pin with pull down, it is used to enter the test mode, pin tio is used in test mode as a digital io, in normal mode it is in tristate. it is re commended to connect pin test to v ss and to leave pin tio open. ST25R3910 36/65 docid029768 rev 2 1.3 registers the 6-bit register addresses below are def ined in hexadecimal notation. the possible addresses range from 00h to 3fh. there are two types of register s implemented in the ST25R3910: ? configuration registers ? display registers the configuration registers are used to conf igure the ST25R3910. they can be read and written (rw) through the spi. the display registers are read only (r); they contain information about the ST25R3910 internal state. table 7. registers map address (hex) main function content type 00 main iso mode definition register rw 01 operation control register rw 02 configuration configuration register 2 rw 03 configuration register 3 (iso-14443a and nfc) rw 04 configuration register 4 (iso-14443b) rw 05 configuration register 5 rw 06 receiver configuration register rw 07 interrupt and associated reporting mask interrupt register rw 08 interrupt register r 09 fifo status register r 0a collision register (iso-14443a only) r 0b number of transmitted bytes register 0 rw 0c number of transmitted bytes register 1 rw 0d adc output a/d output register r 0e antenna calibration antenna calibration register r 0f external trim register rw 10 am modulation depth and antenna driver modulation depth definition register rw 11 modulation depth display register r 12 antenna driver am modulated level definition register rw 13 antenna driver non-modulated level definition register rw 14 nfcip field detection nfcip field detection threshold register rw 15 regulators regulator display register r 16 regulated voltage definition register rw 17 receiver state receiver state display register r docid029768 rev 2 37/65 ST25R3910 55 1.3.1 iso mode de finition register address: 00h type: rw table 8. iso mode definition register (1) bit name default function comments 7nfc (2) 0 1: nfcip-1 0: iso-14443 enables nfcip-1, 106 kbps active communication mode 6 b_a 0 1: iso-14443b 0: iso-14443a applicable if nfc = 0 5tx_rate2 0 tx_rate2 tx_rate1 tx_rate0 bit rate select iso-14443 data rate for transmit. applicable if nfc = 0 4tx_rate10000106 kbps 3tx_rate0 0 001212 kbps 010424 kbps 011848 kbps 1xxrfu 2rx_rate2 0 rx_rate2 rx_rate1 rx_rate0 bit rate select iso-14443 data rate for receive. applicable if nfc = 0 1 rx_rate1 0 0 0 0 106 kbps 0rx_rate0 0 001212 kbps 010424 kbps 011848 kbps 1xxrfu 1. default setting takes place at power-up and after set default command. 2. if nfc=1, both transmit and receive data rates are set to 106 kbps independently from tx and rx setting. ST25R3910 38/65 docid029768 rev 2 1.3.2 operation control register address: 01h type: rw note: receive low power operation reduces the i nput sensitivity in exch ange for lower power consumption. if rx consumption is reduced fr om 10 to 5 ma, 10 ma reader operation is possible. table 9. operation control register (1) bit name default function comments 7en 0 1: enables oscillator and regulator (ready mode) internally or-ed with the en pin 6 rx_en 0 1: enables rx operation - 5 rx_lp 0 1: enables low power receiver op eration receive consumption is reduced 4 tx_en 0 1: enables rf output - 3 nfc_t 0 1: enables initial nfc target mode when rf field is detected, interrupt is sent 2- - not used - 1- - - 0- - - 1. default setting takes place at power-up and after set default command. docid029768 rev 2 39/65 ST25R3910 55 1.3.3 configuration register 2 address: 02h type: rw table 10. configuration register 2 (1) bit name default function comments 7 sing 0 1: only rfo1 driver will be used choose between single and differential antenna driving 6 envi 0 1: input applied to rfi1 is envelope rf envelope input 5 tf2 0 1: reduces first stage gain by 11 db when both bits are set there is a 17 db gain reduction 4 tf1 0 1: reduces first stage gain by 6 db 3 osc 1 0: 13.56 mhz xtal 1: 27.12 mhz xtal selector for crystal oscillator 2 out_cl1 0 out_cl1 out_cl0 mcu_clk selection of clock frequency on mcu_clk output. in case of ?11? mcu_clk output is permanently low. 1 out_cl0 0 003.39 mhz 016.78 mhz 1 0 13.56 mhz 1 1 no output 0 - - not used - 1. default setting takes place at power-up and after set default command. ST25R3910 40/65 docid029768 rev 2 1.3.4 configuration regist er 3 (iso-14443a and nfc) address: 03h type: rw table 11. configuration regi ster 3 (iso-14443a and nfc) (1) bit name default function comments 7 crc_rx 0 1: receive without crc for iso-14443a anticollision. valid only for iso14443a mode, receive without crc is not supported in iso14443b mode. 6 no_par 0 1: no byte parity check when set to 1 parity bits are still detected and removed before received data is put in fifo, but without checking their correctness. 5 p_len3 0 p_len3 p_len2 p_len1 p_len0 reduction modulation pulse reduction, defined in number of 13.56 mhz clock periods. 4 p_len2 0 0 0 0 0 0 3 p_len1 0 0 0 0 1 74 ns 2 p_len0 0 ... ... ... ... ... 1 1 1 1 1106 ns 1- - not used - 0- - - 1. default setting takes place at power-up and after set default command. docid029768 rev 2 41/65 ST25R3910 55 1.3.5 configuration re gister 4 (iso-14443b) address: 04h type: rw table 12. configuration register 4 (iso-14443b) (1) bit name default function comments 7egt2 0 egt2 egt1 egt0 no. of egt egt time defined in number of etu 6egt1 0 0 0 0 0 5egt0 0 001 1 ... ... ... ... 111 6 4 sof_0 0 0: 10 etu 1: 11 etu sof, number of etu with logic 0 (10 or 11) 3 sof_1 0 0: 2 etu 1: 3 etu sof, number of etu with logic 1 (2 or 3) 2 eof 0 0: 10 etu 1: 11 etu eof, number of etu with logic 0 (10 or 11) 1 egt 0 0: no egt after last character 1: egt after each character - 0 - - not used - 1. default setting takes place at power-up and after set default command. ST25R3910 42/65 docid029768 rev 2 1.3.6 configuration register 5 address: 05h type: rw table 13. io configuration register 5 (1) bit name default function comments 7pmd 0 0: am demodulation 1: pm demodulation am/pm demodulation selection 6am 0 0: ook 1: am valid for transparent mode. for iso-14443 and nfc modes, modulation type is set automatically (iso-14443a and nfc is ook, iso-14443b is am, see modulation depth definition register ) 5- - not used - 4- - - 3- - - 2 fifo_lr 0 0: 28 1: 24 fifo water level for receive 1 fifo_lt 0 0: 4 1: 8 fifo water level for transmit 0 - - not used - 1. default setting takes place at power-up and after set default command. docid029768 rev 2 43/65 ST25R3910 55 1.3.7 receiver configuration register address: 06h type: rw table 14. receiver configuration register (1) bit name default function comments 7 agc_en 0 1: agc enabled agc operation mode 6 agc_m 0 1: agc operates on first eight subcarrier pulses 0: agc operates during the whole receive period 5rg2 0 rg2 rg1 rg0 gain reduction gain reduction from 0 to 21 db, in 3 db steps 4rg1 0 000 0 3rg0 0 0 0 1 3 db ... ... ... ... 1 1 1 21 db 2 fs2 0 fs2 fs1 fs0 filter selection (2) comments filter selection is automatically set when iso mode or receive data rate changes (change of iso mode definition register ). after automatic preset filter, selection can be changed by writing these bits. 1fs1 0 000 iso-14443a 106 kbps automatic preset 0 fs0 0 001 iso-14443b 106 kbps 010 iso-14443a/b 212 kbps 011 iso-14443a/b 424 kbps 100 iso-14443a/b 848 kbps 110 424/848 khz subcarriers no automatic preset 111 212 khz subcarrier other combinations not s upported, or used for block testing purposes 1. default setting takes place at power-up and after set default command. 2. filter selection bits are preset also when iso mode or receive data rate change. ST25R3910 44/65 docid029768 rev 2 1.3.8 mask interrupt register address: 07h type: rw 1.3.9 interrupt register address: 08h type: rw table 15. mask interrupt register (1) r bit name default function comments 7 m_osc 0 mask intr when oscillator frequency is stable - 6 m_nfc 0 mask intr due to nfc event - 5 m_wl 0 mask intr due to fifo water level - 4 m_rxs 0 mask intr due to end of receive - 3 m_txe 0 mask intr due to end of transmission - 2 m_err 0 mask intr due to error in receive data coding - 1 m_crc 0 mask intr due to crc error - 0 m_col 0 mask intr due to bit collision - 1. default setting takes place at power-up and after set default command. table 16. interrupt register (1)(2) bit name default function comments 7 i_osc 0 intr when oscillator frequency is stable set after enable 6 i_nfc 0 intr due to nfc event set when nfc_t is 1 and en=0 informing that an rf field has been detected, set when transmission could not be done due to detection of rf field during rf collision avoidance 5 i_wl 0 intr due to fifo water level set during receive, informing that fifo is almost full and has to be read out. set during transmit, informing that fifo is almost empty and that additional data has to be sent. 4 i_rxs 0 intr due to end of receive - 3 i_txe 0 intr due to end of transmission - 2 i_err 0 intr due to error in receive data coding includes parity error and framing error 1 i_crc 0 intr due to crc error - 0 i_col 0 intr due to bit collision valid only for iso-14443a 1. default setting takes place at power-up and after set default command. 2. after register is read, its content is set to 0. docid029768 rev 2 45/65 ST25R3910 55 1.3.10 fifo status register address: 09h type: rw 1.3.11 collision regi ster (iso-14443a only) address: 0ah type: r table 17. fifo status register (1) bit name default function comments 7 fifo_b5 0 number of bytes (binary coded) in the fifo that have not been read out valid range is from 000000 to 100000 6 fifo_b4 0 5 fifo_b3 0 4 fifo_b2 0 3 fifo_b1 0 2 fifo_b0 0 1 fifo_ovr 0 1: fifo overflow - 0 rx_act 0 1: reception active this bit is set to 1 when the start of a tag message is detected, and stays high until the end of the tag message is detected. 1. default setting takes place at power-up, after set default and after clear commands. table 18. collision regi ster (iso-14443a only) (1) bit name default function comments 7 c_byte3 0 number of full bytes before the byte where the collision happened - 6 c_byte2 0 5 c_byte1 0 4 c_byte0 0 3 c_bit2 0 number of bits before the bit where the collision happened - 2 c_bit1 0 1c_bt0 0 0 rfu 0 not used - 1. default setting takes place at power-up, after set default and after clear content commands. ST25R3910 46/65 docid029768 rev 2 1.3.12 number of transm itted bytes register 0 address: 0bh type: rw 1.3.13 number of transm itted bytes register 1 address: 0ch type: rw table 19. number of transmitted bytes register 0 (1) bit name default function comments 7ntx1 0 number of bytes to be transmitted in one command (lsb bits) maximum supported number of bytes is 1023 6ntx0 0 5nbtx2 0 number of bits in the split byte, 000 means that the split byte is actually a complete byte applicable only to iso-14443a bit oriented anticollision frame in case last byte is a split byte 4nbtx1 0 3nbtx0 0 2 - 0 not used - 1 frm4 (2) 0 1: 4bit response frame has to be set to 1 when 4bit response frame is expected (mifare ultralight) 0antcl (2) 0 1: iso-14443 anticollision frame has to be set to 1 when iso-14443a bit-oriented anticollision frame is sent 1. default setting takes place at power-up, after set default and after clear commands. 2. cleared after transmission. table 20. number of transmitted bytes register 1 (1) bit name default function comments 7ntx9 0 number of bytes to be transmitted in one command (msb bits) maximum supported number of bytes is 1023 6ntx8 0 5ntx7 0 4ntx6 0 3ntx5 0 2ntx4 0 1ntx3 0 0ntx2 0 1. default setting takes place at power-up, after set default and after clear commands. docid029768 rev 2 47/65 ST25R3910 55 1.3.14 a/d output register address: 0dh type: r 1.3.15 antenna calibration register address: 0eh type: r table 21. a/d output register (1) bit name default function comments 7ad7 - displays result of a/d conversion - 6ad6 - 5ad5 - 4ad4 - 3ad3 - 2ad2 - 1ad1 - 0ad0 - 1. at power-up and after set default command content of this register is set to 0. table 22. antenna calibration register (1) bit name default function comments 7tri_3 -msb this register stores result of calibrate antenna command. lc trim switches are defined by data written in this register in case trim_s = 0. a bit set to 1 indicates that the corresponding transistor on trim1_x and trim2_x pin is switched on. 6tri_2 - - 5tri_1 - - 4tri_0 -lsb 3 tri_err - 1: antenna calibration error set when calibrate antenna sequence has not been able to adjust resonance 2- - not used - 1- - 0- - 1. at power-up and after set default command content of this register is set to 0. ST25R3910 48/65 docid029768 rev 2 1.3.16 external trim register address: 0fh type: rw table 23. external trim register (1) bit name default function comments 7 trim_s 0 0: lc trim switches are defined by result of calibrate antenna command 1: lc trim switches are defined by bits tre_x written in this register defines source of driving switches on trimx pins 6tre_3 0msb lc trim switches are defined by data written in this register when trim_s=1. a bit set to 1 indicates that the corresponding transistor on trim1_x and trim2_x pin is switched on. 5tre_2 0 - 4tre_1 0 - 3tre_0 0lsb 2- - not used - 1- - - 0- - - 1. default setting takes place at power-up and after set default command. docid029768 rev 2 49/65 ST25R3910 55 1.3.17 modulation dept h definition register address: 10h type: rw 1.3.18 modulation de pth display register address: 11h type: r table 24. modulation depth definition register (1) bit name default function comments 7am_s 0 0: am modulated level is defined by bits mod5 to mod0. level is adjusted automatically by calibrate modulation depth command 1: am modulated level is defined by bits dram7 to dram0. - 6 mod5 0 msb see section 1.2.14: am modulation depth: definition and calibration on page 30 for details about am modulation lavel definition. 5 mod4 0 - 4 mod3 0 - 3 mod2 0 - 2 mod1 0 - 1 mod0 0 lsb 0 - - not used - 1. default setting takes place at power-up and after set default command. table 25. modulation depth display register (1) bit name default function comments 7 md_7 0 msb displays result of calibrate modulation depth command. antenna drivers are composed of 8 binary weighted segments. bit md_x set to 1 indicates that this particular segment will be disabled during am modulated state. 6 md_6 0 - 5 md_5 0 - 4 md_4 0 - 3 md_3 0 - 2 md_2 0 - 1 md_1 0 - 0 md_0 0 lsb 1. at power-up and after set default command content of this register is set to 0. ST25R3910 50/65 docid029768 rev 2 1.3.19 antenna driver am modu lated level definition register address: 12h type: rw 1.3.20 antenna driver non-modul ated level definition register address: 13h type: rw table 26. antenna driver am modulated level definition register (1) bit name default function comments 7 dram7 0 msb antenna drivers are composed of 8 binary weighted segments. setting one of dram bits to 1 will disable the corresponding segment during am modulated state in case am_s bit is set to 1. 6 dram6 0 - 5 dram5 0 - 4 dram4 0 - 3 dram3 0 - 2 dram2 0 - 1 dram1 0 - 0 dram0 0 lsb 1. at power-up and after set default command content of this register is set to 0. table 27. antenna driver non-modulated level definition register (1) bit name default function comments 7 droff7 0 msb antenna drivers are composed of 8 binary weighted segments. setting one of droff bits to 1 will disable the corresponding segment during normal non-modulated operation. 6droff6 0 - 5droff5 0 - 4droff4 0 - 3droff3 0 - 2droff2 0 - 1droff1 0 - 0droff0 0lsb 1. at power-up and after set default command content of this register is set to 0. docid029768 rev 2 51/65 ST25R3910 55 1.3.21 nfcip field det ection threshold register address: 14h type: rw table 28. nfcip field detection threshold register (1) bit name default function comments 7 trg_l3 0 target activation level msb threshold used to detect pr esence of interrogator magnetic field. see table 29 for threshold definition. 6 trg_l2 0 - 5 trg_l1 0 - 4 trg_l0 0 target activation level lsb 3 trg_t3 0 collision avoidance threshold msb threshold used to detect presence of external field during collision avoidance. see table 30 for threshold definition. 2 trg_t2 0 - 1 trg_t1 0 - 0 trg_t0 0 collision avoidance threshold lsb 1. at power-up and after set default command content of this register is set to 0. table 29. target activation threshold as seen on rfi1 input trg_l3 trg_l2 trg_l1 trg_l0 target activation threshold voltage x 0 0 0 forbidden (measurement is deactivated) 0001 590 mv pp 0010 420 mv pp 0011 350 mv pp 1001 350 mv pp 0100 300 mv pp 0101 265 mv pp 1010 265 mv pp 0110 235 mv pp 0111 220 mv pp 1011 220 mv pp 1100 190 mv pp 1101 175 mv pp 1110 155 mv pp 1111 145 mv pp ST25R3910 52/65 docid029768 rev 2 table 30. collision avoidance threshold as seen on rfi1 input rfe_3 rfe_2 rfe_1 rfe_0 collision avoidance threshold voltage x 0 0 0 forbidden (measurement is deactivated) 0001 50 mv pp 0010 67 mv pp 0011 88 mv pp 0100 120 mv pp 1001 145 mv pp 0101 172 mv pp 1010 185 mv pp 0110 240 mv pp 1011 255 mv pp 1100 340 mv pp 0111 350 mv pp 1101 480 mv pp 1110 700 mv pp 1111 1080 mv pp docid029768 rev 2 53/65 ST25R3910 55 1.3.22 regulator display register address: 15h type: r 1.3.23 regulated voltage definition register address: 16h type: rw table 31. regulators display register (1) bit name default function comments 7 reg_3 0 msb displays actual regulated voltage when regulator is operating. in power-down mode its content is forced to 00h. see table 33 for definition. 6 reg_2 0 - 5 reg_1 0 - 4 reg_0 0 lsb 3- 0 not used - 2- 0 - 1- 0 - 0- 0 - 1. at power-up and after set default command regulated voltage is set to 3.4 v (maximum value). table 32. regulated voltage definition register (1) bit name default function comments 7 reg_s 0 0: regulated voltages are defined by result of adjust regulators command 1: regulated voltages are defined by rege_x bits written in this register defines mode of regulator voltage setting. 6 rege_3 0 msb external definition of regulated voltage. refer to table 33 for definition. 5 rege_2 0 - 4 rege_1 0 - 3 rege_0 0 lsb 2- 0 not used - 1- 0 - 0- 0 - 1. default setting takes place at power-up and after set default command. ST25R3910 54/65 docid029768 rev 2 table 33. regulated voltages reg_3 rege_3 reg_2 rege_2 reg_1 rege_1 reg_0 rege_0 regulated voltage (v) 11113.4 11103.3 11013.2 11003.1 10113.0 10102.9 10012.8 10002.7 01112.6 01102.5 01012.4 other combinations 2.4 docid029768 rev 2 55/65 ST25R3910 55 1.3.24 receiver st ate display register address: 17h type: r table 34. receiver state display register (1) bit name default function comments 7 rssi_3 0 msb stores peak value of am channel rssi measurement. automatically cleared at beginning of tag message and with clear rssi command. 6 rssi_2 0 - 5 rssi_1 0 - 4 rssi_0 0 lsb 3 oscok/rfp 0 unlatched osc_ok flag when nfc=0 target activation detector output when nfc=1 - 2gr_2 0 gr_2 gr_1 gr_0 gain reduction displays status of receiver gain reduction (result of agc, gain reduction setting and squelch command). 1gr_10000 0 0gr_0 0 001 3 db ... ... ... ... 1 1 1 21 db 1. at power-up and after set default command content of this register is set to 0. table 35. rssi rssi_3 rssi_2 rssi_1 rssi_0 typi cal signal on rfi1 (mv rms ) 0000 0 to 0.28 0 0 0 1 0.28 to 0.35 0 0 1 0 0.35 to 0.45 0 0 1 1 0.45 to 0.57 0 1 0 0 0.57 to 0.74 0 1 0 1 0.74 to 0.95 0 1 1 0 0.95 to 1.21 0 1 1 1 1.21 to 1.56 1 0 0 0 1.56 to 2.00 1 0 0 1 2.00 to 2.55 1 0 1 0 2.55 to 3.27 1 0 1 1 3.27 to 4.20 1 1 0 0 4.20 to 5.37 1 1 0 1 5.37 to 6.88 1 1 1 0 6.88 to 8.80 1111 > 8.80 pinouts and pin description ST25R3910 56/65 docid029768 rev 2 2 pinouts and pin description the ST25R3910 pin and pad assignments are described in figure 12 . figure 12. ST25R3910 qfn32 pinout (1) 1. the above figure shows the package top view. 0 6 9 7 , 2 7 ( 6 7 ( 1 ; 7 2 ; 7 , 9 6 1 b ' 9 6 3 b $ 9 ' ' 9 6 3 b 5 ) 5 ) 2 5 ) 2 9 6 1 b 5 ) 7 5 , 0 b 7 5 , 0 b 7 5 , 0 b 7 5 , 0 b $ * ' 5 ) , 5 ) , 9 6 6 7 5 , 0 b 7 5 , 0 b 7 5 , 0 b 7 5 , 0 b 6 ( 1 6 & / . 6 ' $ 7 $ , 6 ' $ 7 $ 2 0 & 8 b & / . , 1 7 5 9 6 1 b $ $ ' b , 1 4 ) 1 table 36. ST25R3910 pin definitions - qfn32 package pin number pin name pin type description 1 tio digital bidirectional test io pin 2 en digital input with pull down enable input 3 test test input 4 xto analog output xtal oscillator output 5 xti analog input xtal oscillator input 6 vsn_d supply pad digital ground 7 vsp_a analog input/output analog supply, regulator output 8 vdd supply pad external positive supply 9 vsp_rf analog input/output supply, regulator out put for antenna drivers 10 rfo1 analog output antenna driver output 11 rfo2 12 vsn_rf supply pad ground of antenna drivers docid029768 rev 2 57/65 ST25R3910 pinouts and pin description 57 13 trim1_3 analog input input to trim antenna resonant circuit 14 trim2_3 15 trim1_2 16 trim2_2 17 trim1_1 18 trim2_1 19 trim1_0 20 trim2_0 21 vss supply pad ground, die subs trate potential 22 rfi1 analog input receiver input 23 rfi2 24 agd analog i/o analog reference voltage 25 ad_in analog input a/d converter input 26 vsn_a supply pad analog ground 27 intr digital output interrupt request output 28 mcu_clk microcontroller clock output 29 sdatao digital output / tristate serial peripheral interface data output 30 sdatai digital input serial peripheral interface data input 31 sclk serial peripheral interface clock 32 sen serial peripheral interface enable 33 vsub supply ground, die substrate pot ential, connected to v ss on pcb table 36. ST25R3910 pin definitions - qfn32 package (continued) pin number pin name pin type description electrical characteristics ST25R3910 58/65 docid029768 rev 2 3 electrical characteristics 3.1 absolute maximum ratings stresses beyond those listed table 37 , table 38 and table 39 may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions beyond those indicated in section 3.2: operating conditions is not guaranteed. exposure to absolute maximum rating conditions for extended periods may af fect device reliability. table 37. electrical parameters symbol parameter min max unit comments v dd dc supply voltage -0.5 5.0 v - v in input pin voltage (all except trim pins) -0.5 5.0 v - v intrim input pin voltage trim pins -0.5 30 v - i scr input current (latch-up immunity) -100 100 ma norm: jedec 78 table 38. electrostatic discharge symbol parameter min max unit comments esd electrostatic discharge 2 - kv mil 883 e method 3015 (human body model) table 39. temperature ranges and storage conditions symbol parameter min max unit comments t strg storage temperature -55 125 c - t body package body temperature - 260 c the refllow peak soldering temperature (body temperature) is specified according to ipc/jedec j-std-020 ?moisture/reflow sensitivity classification for non-hermetic so lid state surface mount devices.? rh nc relative humidity non-condensing 585% - msl moisture sensitivity level 3 - represents a max. floor life time of 168 h docid029768 rev 2 59/65 ST25R3910 electrical characteristics 60 3.2 operating conditions all defined tolerances for external components in this specification need to be assured over the whole operating conditions range and over lifetime. 3.3 dc/ac characteristics for digital inputs and outputs 3.3.1 cmos inputs valid for input pins en, sen , sdatai, test and sclk. 3.3.2 cmos outputs valid for output pins sdatao, intr and mcu_clk. table 40. operating conditions symbol parameter min max unit comments v dd positive supply voltage 2.4 3.6 v in case power supply is lower than 2.6 v, pssr cannot be improved using internal regulators (minimum regulated voltage is 2.4 v). v ss negative supply voltage 0 0 v - v intrim input pin voltage trim pins -30v - t amb ambient temperature -40 85 c - table 41. cmos inputs symbol parameter min typ max unit v ih high level input voltage 0.7 * v dd --v v il low level input voltage - - 0.3 * v dd v i leak input leakage current - - 2 a r pd pull down resistance (pad en) - 100 - k ? table 42. cmos outputs symbol parameter conditions min typ max unit v oh high level output voltage i source = 1ma 0.9 * v dd --v v ol low level output voltage i sink = 1ma - - 0.1 * v dd v c l capacitive load - 0 - 50 pf r o output resistance - 0 250 550 ? electrical characteristics ST25R3910 60/65 docid029768 rev 2 3.4 electrical specifications v dd = 3.3 v, temperature 25 c unless noted otherwise. table 43. electrical specifications symbol parameter min typ max unit comments i pd supply current in power-down mode -0.32 a - i nfct supply current in initial nfc target mode -3.57 a - i rd supply current in ready mode - 2 3 ma 13.56 mhz xtal, mcu_clk disabled i al supply current, receiver active - 5 7 ma i lp supply current, receiver active, low power mode -35ma r rfo rfo1 and rfo2 driver output resistance -1.54 ? i rfo =10 ma, all segments on v rfi rfi input sensitivity (1) -0.5-mv rms f sub =848 khz v rfi_lp rfi input sensitivity, low power receiver mode -1.5-mv rms r rfi rfi input resistance - 10 - k ? - v por power on reset voltage 1.0 1.4 2.4 v - v agd agd voltage 1.4 1.5 1.6 v - v ar regulator drop - 250 - mv after execution of direct command adjust regulators t osu oscillator start-up time - 0.7 - ms 13.56 mhz or 27.12 mhz crystal r s =50 ? max load capacitance according to crystal specification 1. amplitude of carrier signal at rfi inputs is 2.5 v pp , maximum amplitude is 3 v pp . docid029768 rev 2 61/65 ST25R3910 package information 62 4 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at www.st.com . ecopack ? is an st trademark. 4.1 qfn32 package information the ST25R3910 is available in a 32-pin qfn (5 mm x 5 mm) package (see figure 13 ). dimensions are detailed in table 44 . figure 13. qfn32 package outline 1. dimensioning and tolerances conform to asme y14.5m-1994. 2. co-planarity applies to the exposed heat slug as well as to the terminal. 3. radius on terminal is optional. 4. n is the total number of terminals. 5. this drawing is subjec t to change without notice. package information ST25R3910 62/65 docid029768 rev 2 table 44. qfn32 5 mm x 5 mm dimensions (1) 1. all dimensions are in mm. all angles are in degrees. symbol (as specified in figure 13 ) min. typ. max. a 0.80 0.90 1.00 a1 0 0.02 0.05 a2 - 0.65 1.00 a3 - 0.20 - l 0.35 0.40 0.45 q0o-14o b 0.18 0.25 0.30 d - 5.00 (with bsc) - e - 5.00 (with bsc) - e - 0.50 (with bsc) - d2 3.40 3.50 3.60 e2 3.40 3.50 3.60 d1 - 4.75 (with bsc) - e1 - 4.75 (with bsc) - aaa - 0.15 - bbb - 0.10 - ccc - 0.10 - ddd - 0.05 - eee - 0.08 - fff - 0.10 - n (2) 2. total number of terminals. 32 docid029768 rev 2 63/65 ST25R3910 part numbering 64 5 part numbering note: parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st char ge. in no event, st wi ll be liable for any customer usage of these engineering samples in production. st quality has to be contacted prior to any decision to use these engineering samples to run qualification activity. table 45. ordering information scheme example: st25 r 39 10 - b qf t device type st25 = nfc/rfid tags and readers product type r = reader frequency range 39 = hf products product feature 10 = mid range reader / nfc initiator temperature range b = -40 c to 85 c package/packaging qf = 32-pin qfn (5 mm x 5 mm) tape and reel t = 4000 pcs/reel revision history ST25R3910 64/65 docid029768 rev 2 6 revision history table 46. document revision history date revision changes 21-nov-2016 1 initial release. 08-feb-2017 2 updated section 1.1.2: receiver , section 1.1.3: phase and amplitude detector , section 1.1.4: a/d converter , section 1.1.6: quartz crystal oscillator , section 1.1.7: power supply regulators , section 1.1.8: por and bias , squelch and rssi . updated table 45: ordering information scheme . docid029768 rev 2 65/65 ST25R3910 65 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2017 stmicroelectronics ? all rights reserved |
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